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七段显示译码器vhdl程序

来源：艾特贸易2017-03-18

简介七段显示译码器vhdl程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ymq is port ( num:in std_logic_vector(3 downto 0); dout:out std_logic_vector(6 downto 0) ); end

七段显示译码器vhdl程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ymq is
port
(
num:in std_logic_vector(3 downto 0);
dout:out std_logic_vector(6 downto 0)
);
end ymq;

architecture a1 of ymq is
begin
with num select
dout<="1111110" when "0000",
"0110000" when "0001",
"1101101" when "0010",
"1111001" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1111011" when "1001",
"0000000" when others;
end a1;